1. Field of the Invention
This invention generally relates to a semiconductor package, and more particularly to a ball grid array (BGA) semiconductor package with improved thin substrate strength and electric performance.
2. Description of the Related Art
As the need for lighter and more complicated semiconductor devices becomes greater day by day, the semiconductor chips have become more and more complex thereby requiring more electrical connections. Therefore, the ball grid array (BGA) has been developed by the semiconductor chip packaging industry to meet these needs.
FIG. 1 depicts a conventional BGA semiconductor chip package 100 including a chip 101 attached on a substrate 102 having a dielectric layer 101a. The chip pads on the active surface of the chip 101 are connected to conductive traces 101c disposed on the upper surface 101b of the dielectric layer 101a by bonding wires 103 and the conductive traces 101c are electrically connected through the through holes 107 to the solder ball pads 101f disposed on the lower surface 101d of the dielectric layer 101a. Each solder ball pads 101f has a solder ball 104 mounted thereon for electrical connection to outer circuit, such as a printed circuit board. A package body 105 encapsulates the chip 101, bonding wires 103 and the substrate 102.
The dielectric layer 101a of the substrate 102 is generally made of fiberglass reinforced bismaleimide-triazine (BT) resin, FR-4 fiberglass reinforced BT epoxy resin or polyimide and the thickness of the substrate 102 is about 0.56 mm. A copper die pad 108 is disposed on the central surface of the substrate 102 for carrying the chip 101. The through holes (vias) 107 are arranged around the die pad 108.
However, the overall volume of the above BGA semiconductor chip package 100 is too large to meet the packaging requirements for high density semiconductor chip. Accordingly, the packaging industry further develops a chip sized package (CSP) technology to meet the packaging requirements for high density semiconductor chip. Generally, the overall dimension of the chip sized package is smaller than 1.2 times of the chip dimension so as to increase the packaging density.
FIG. 2 illustrates a conventional CSP semiconductor chip package 200 including a chip 201 attached on a substrate 202 having a dielectric layer 202a. The chip pads 201a on the active surface of the chip 201 are connected to conductive traces 202c disposed on the upper surface 202b of the dielectric layer 202a by bonding wires 203 and the conductive traces 202c are electrically connected through the through holes (vias) 207 to the solder ball pads 202f disposed on the lower surface 202d of the dielectric layer 202a. Each solder ball pads 202f has a solder ball 204 mounted thereon for electrical connection to outer circuit, such as a printed circuit board. A package body 205 encapsulates the chip 201, bonding wires 203 and the substrate 202. According to the CSP semiconductor chip package 200, the area surrounded by the solder balls is usually smaller than the area of the chip 201.
According to the CSP semiconductor chip package 200 as shown in FIG. 2, the thickness of the substrate 202 is about 0.36 mm or less than 0.36 mm and the through holes (vias) 207.of the substrate 202 are arranged within the periphery of the chip 201. At room temperature, the Storage Modulus (Exe2x80x2) of the fiberglass reinforced bismaleimide-triazine (BT) resin for the substrate is about 7,000-9,000 MPa, while the Young""s Modulus (E) of copper for the plated through holes (vias) 207 is about 110,000 MPa. During resin molding (about 175xc2x0 C.), the Storage Modulus (Exe2x80x2) of the BT substrate is about 2,000-3,000 MPa, while the Young""s Modulus (E) of copper for the plated through holes (vias) 207 is about 103,000 MPa.
Therefore, during resin molding (about 175xc2x0 C.), the ratio of the copper""s Young""s Modulus (E) to the BT""s Storage Modulus (Exe2x80x2) increases from 15 to 500 such that the BT substrate 202 without vias 207 is relatively softer than the BT substrate 202 with vias 207 and the area of BT substrate 202 without vias 207 is unable to provide sufficient strength for supporting chip 201. Besides, since the chip 201 is not supported by the die pad, in the CSP package, stress caused by molding pressure will exert on the edge 201b of the chip 201 and the chip will crack at the edge 201b area. This will lower the yield for production. Besides, the thin substrate 202 is susceptible to deform due to temperature fluctuation during post-curing process, which will result in warpage for the semiconductor package. Furthermore, since the ground plane for the conventional substrate 202 is relative small, it is difficult to achieve optimal design for the return current path and impedance matching control to reduce signal coupling and noise.
Accordingly, there is a need for the packaging industry for eliminating the die crack, warpage and electric problems for the chip sized package with thin substrate.
It is a primary object of the present invention to provide a ball grid array (BGA) semiconductor package with improved thin substrate strength and electric performance, wherein at least one metal reinforced layer is provided at the lower surface of the substrate to enhance the strength thereof so as to prevent the die from cracking during packaging process.
It is a secondary object of the present invention to provide a ball grid array (BGA) semiconductor package with improved thin substrate strength and electric performance, wherein at least one metal reinforced layer is provided at the lower surface of the substrate as a ground plane to improve the electrical performance of the BGA semiconductor package.
It is another object of the present invention to provide a method for manufacturing a ball grid array (BGA) semiconductor package with improved thin substrate strength and electric performance, wherein at least one metal reinforced layer is provided at the lower surface of the substrate to enhance the strength thereof so as to prevent the die from cracking during packaging process.
It is a further object of the present invention to provide a method for manufacturing a ball grid array (BGA) semiconductor package with improved thin substrate strength and electric performance, wherein at least one metal reinforced layer is provided at the lower surface of the substrate as a ground plane to improve the electrical performance of the BGA semiconductor package.
To achieve the above objects, the present invention disposes at least one metal reinforced layer, preferably a copper mesh layer, at the lower surface of the thin substrate around the solder balls to reinforce the strength of the thin substrate. With reinforced strength, the thin substrate is not susceptible to deform due to temperature fluctuation during packaging process, and thus the warpage for the semiconductor package is significantly eliminated. The present invention further disposes at least one metal reinforced layer, preferably a copper mesh layer, at the upper surface of the thin substrate around the vias and traces to reinforce the strength of the thin substrate. When the chip is mounted on the substrate, the copper mesh lies under the edges of the chip for supporting the chip during molding process such that the die crack problem is eliminated.
According to another aspect of the present invention, the metal reinforced layer at the lower surface of the thin substrate is functioned as a ground plane for the ball grid array (BGA) semiconductor package for better grounding effect. Since the solder balls are concentrated at the central portion of the lower surface of the thin substrate, there is larger area for the metal reinforced layer, thereby providing an optimal design for the return current path and impedance matching control. Besides, the solder balls connecting to the power source can be disposed close to the metal reinforced layer so as to reduce the signal coupling, and the solder balls connecting to the signal lines can be disposed close to the metal reinforced layer so as to increase the loading capacitance. In high frequency application, the metal reinforced layer also can reduce the noise and cross talk among the signal lines of the ball grid array (BGA) semiconductor package. Accordingly, the present invention significantly improves the electrical performance for the ball grid array (BGA) semiconductor package.